Low Power High Speed Sense Amplifier for CMOS SRAM
Автор:Sakshi Rajput Год: 2012 Издание:LAP Lambert Academic Publishing Страниц: 64 ISBN: 9783659242984 One of the major issues in the design of SRAMs is the memory access time (or speed of read operation). For having high performance SRAMs, it is essential to take care of the read speed both in the cell-level design and in the design of a clever sense amplifier. Sense amplifiers are one of the most critical circuits in the organization of CMOS memories. Their performance strongly influences both memory access time and overall memory power consumption. High density memories commonly come with increased bit line parasitic capacitance. These large capacitance slow down voltage sensing and makes bit line voltage swings energy-consuming, which result in slower more power hungry memories. Need for larger memory capacity, higher speed, and lower power dissipation.In this work, design of low power high speed sense amplifier for CMOS SRAMs has been done. It has to sense the lowest possible signal swing from the SRAMs bit lines and its response time should be very fast while keeping...
